Senior ASIC Verification Engineer

Located in Irvine, CA or San Jose, CA

Description:

Highly visible opportunity for a senior to principal level ASIC functional verification engineer to join a growing Design Verification.

You will be responsible for the development of leading edge verification methodologies and their timely and successful deployment.

Required Skills & Experience:

  • Pseudo-random, functional coverage verification methodologies
  • SystemVerilog class libraries such as UVM (Universal Verification Methodology), OVM (Open
    Verification Methodology) or VMM (Verification Methodology Manual )

Desired Skills:

  • Framer experience with SONET or OTN
  • Networking domain knowledge (e.g. Ethernet, ATM, SONET, GFP, OTN)
  • SVA, PSL or OVL assertions
  • SystemC or C++ experience
  • Formal model checking tools (e.g. Cadence IFV, Jasper)
  • DSP is a plus

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