Located in Irvine, CA
Responsibilities:
- Validate, design and develop complex standard cells that significantly boost circuit performance and optimize dynamic/static power consumption in advanced technologies
- Engage with design teams to understand new library cell requirements, with PPA benefits
- Validate and deliver a complete stdcells design kit or memory compiler to ASIC design team
- Develop optimal circuit solutions that enable better design performance, with improved area/power tradeoffs
- Engage with timing teams, chip level designers, review flow requirements such as synthesis, static timing analysis, crosstalk, EMIR, P&R requirements
Required Skills:
- Must understand complete library design flow, Liberty Formats, Variation Formats, P&R/timing requirements of library, DFT/testing aspect of the design
- Ability to run spectre or spice simulations and debug circuit issues
- Ability to write verilog models and run verilog simulations for stdcells and memory
- Working experience with std cell and memory layout, familiarity with reviewing DRM, DRC/LVS results
- Scripting in Perl and TCL experience
- Familiarity with Overall ASIC Design Flow
- Familiarity with Timing Constraints
- Familiarity with Common issues in 28nm and advanced nodes a plus.
- 5 years of characterization, circuit design & QA experience of Stdcells and Memory Design Kits
- BSEE / MSEE is required