Senior ASIC Design Engineer

Located in Irvine, CA or San Diego, CA


Be solely responsible for  the design and development of multiple ASIC blocks in communications/digital signal processing (DSP) IC products.  Work with systems engineering and product marketing to help design specifications, define block architectures, and execute and and verify the design.

Required Skills:

  • Should be familiar with at least one of the two areas below:
    • Communications/DSP algorithm and efficient implementations.
    • System-on-the-chip architectures (CPU, standard bus structure, memory interface, power domains, clock domains).
  • Knowledge and hands-on experience from industry ASIC design flow including RTL coding, debugging/verification, synthesizing and supporting timing closure.

Required Experience:

  • Design experience in Communications/DSP building blocks and/or SOC functional modules
  • Experience with  design tools such as NCSIM (and/or VCS), Cadence RC or Synopsys DC compiler.
  • Experience with multiple IC tape-out in industry.
  • Experience in chip bring up and performance measurement for IC and systems in laboratory to characterize and debug building blocks.
  • MS in EE with 8+ years of experience or Ph.D. in EE with 5+ years of experience.

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